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FEMTOCLOCKSTM VCXO-PLL FREQUENCY GENERATOR FOR WIRELESS INFRASTRUCTURE EQUIPMENT
ICS813078I
General Description
The ICS813078I is a member of the HiperClocks family of high performance clock solutions from IDT. HiPerClockSTM The ICS813078I a PLL based synchronous clock solution that is optimized for wireless infrastructure equipment where frequency translation and jitter attenuation is needed.
Features
* * * * * * * * * * * * * * * *
Nine outputs, organized in three independent output banks with differential LVPECL and single-ended outputs One differential input clock can accept the following differential input levels: LVDS, LVPECL, LVHSTL One single-ended clock input Frequency generation optimized for wireless infrastructure Attenuates the phase jitter of the input clock signal by using low-cost pullable fundamental mode crystal (XTAL) Internal Femtoclock frequency multiplier stage eliminates the need for an expensive external high frequency VCXO LVCMOS levels for all control I/O RMS phase jitter @ 122.88MHz, using a 30.72MHz crystal (12kHz to 20MHz): 1.1ps rms (typical) RMS phase jitter @ 61.44MHz, using a 30.72MHz crystal (12kHz to 20MHz): 0.97ps rms (typical) VCXO PLL bandwidth can be optimized for jitter attenuation and reference frequency tracking using external loop filter components PLL fast-lock control PLL lock detect output Absolute pull range is +/-50 ppm Full 3.3V supply voltage -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
ICS
The device contains two internal PLL stages that are cascaded in series. The first PLL stage attenuates the reference clock jitter by using an internal or external VCXO circuit. The internal VCXO requires the connection of an external inexpensive pullable crystal (XTAL) to the ICS813078I. This first PLL stage (VCXO PLL) uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The output of the first stage VCXO PLL is a stable and jitter-tolerant 30.72MHz reference input for the second PLL stage. The second PLL stage provides frequency translation by multiplying the output of the first stage up to 491.52MHz or 614.4MHz. The low phase noise characteristics of the VCXO-PLL clock signal is maintained by the internal FemtoClockTMPLL, which requires no external components or complex programming. Two independently configurable frequency dividers translate the internal VCO signal to the desired output frequencies. All frequency translation ratios are set by device configuration pins. Supported input reference clock frequencies: 10MHz, 12.8MHz, 15MHz, 15.36MHz, 20MHz, 30.72MHz, 61.44MHz, and 122.88MHz Supported output clock frequencies: 30.72MHz, 38.4MHz, 61.44MHz, 76.8MHz, 122.88MHz, 153.6MHz, 245.76MHz, 491.52MHz, and 614.4MHz
Pin Assignment
VEE XTAL__IN XTAL_OUT QC1 VEE QC2 VCCO_CMOS QC3 VEE VCC MF LOCK VEE QC0 VCCO_CMOS nc
LF1 LF0 ISET nc FLM VCC VCC CLK1 REF_SEL nMR CLK0 nCLK0 VEE NA1 NA0 NB1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 3 46 4 45 5 44 6 43 64-Lead TQFP, E-Pad 7 42 10mm x 10mm x 1mm 8 41 package body 9 40 Y Package 10 39 11 38 12 37 13 36 14 35 1 2 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NB0 NC1 NC0 R2 R1 R0 BYPASS1 BYPASS0 nc nc VCCA nSTOPA nSTOPB nSTOPC QB1 nQB1
nc nc VCCO nQA0 QA0 VEE nQA1 QA1 VCCO nQA2 QA2 VCC VEE nQB0 QB0 VCCO
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Block Diagram
XTAL_IN LF0 ISET LF1 XTAL_OUT fXTAL = 30.72MHz
LOCK nSTOPA
fOUT
QA0 nQA0 QA1 nQA1 QA2 nQA2
fREF
CLK0 nCLK0 CLK1
fVCXO fPD fVCO
11 10 Femto PLL /16, /20
NA /2, /4 /5, /8
0 0 1
P /1, /2, /4, /5, /125
PD
CP
VCXO
0x NB /1, /4 /5, /8 QB0 nQB0 QB1 nQB1
REF_SEL 3
MV /1, /2, /12, /192, /256, /384 LUT Multiplier
R[2:0] FLM MF BYPASS[1:0] nSTOPB
Internal VCXO
2
QC0 NC /4, /5, /8, /16 NA[1:0] NB[1:0] NC[1:0] nMR nSTOPC QC1 QC2 QC3
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Table 1. Pin Descriptions
Number 1 2 3 4, 25, 26, 47, 48, 49 5 6, 7, 37, 61 8 9 10 11 12 13, 36, 43, 50, 54, 58, 64 14. 15 16, 17 18, 19 20, 21, 22 23, 24 27 28 29 30 31, 32 33, 40, 46 34, 35 38, 39 41, 42 44, 45 Name LF1 LF0 ISET nc FLM VCC CLK1 REF_SEL nMR CLK0 nCLK0 VEE NA1, NA0 NB1, NB0 NC1, NC0 R2, R1, R0 BYPASS1, BYPASS0 VCCA nSTOPA nSTOPB nSTOPC QB1, nQB1 VCCO QB0, nQB0 QA2, nQA2 QA1, nQA1 QA0, nQA0 Analog Input Analog Output Analog Unused Input Power Input Input Input Input Input Power Input Input Input Input Input Power Input Input Input Output Power Output Output Output Output Pullup Pullup Pullup Pulldown Pulldown Pulldown Pulldown Pullup Pulldown Pulldown Pullup Pulldown Pullup/ Pulldown Pulldown Type Description Input from external loop filter. VCXO control voltage input. Output to external loop filter. Charge pump output. Charge pump current-settings pin. No connect. VCXO-PLL fast lock mode. See Table 3H. LVCMOS/LVTTL interface levels. Power supply pins for LVPECL outputs. Single-ended reference clock input. LVCMOS/LVTTL interface levels. Selects the input reference clock. See Table 3F. LVCMOS/LVTTL interface levels. Master reset. See Table 3I. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Negative supply pins. Femto-PLL output-divider for QAn/nQAn outputs. See Table 3B. LVCMOS/LVTTL interface levels. Femto-PLL output-divider for QBn/nQBn outputs. See Table 3C. LVCMOS/LVTTL interface levels. Femto-PLL output-divider for QCn outputs. See Table 3D. LVCMOS/LVTTL interface levels. VCXO-PLL pre-divider and VCXO multiplier selection. See Table 3A. LVCMOS/LVTTL interface levels. PLL mode selections. See Table 3G. LVCMOS/LVTTL interface levels. Analog supply pin. Output clock stop for Bank A. See Table 3J. LVCMOS/LVTTL interface levels. Output clock stop for Bank B. See Table 3K. LVCMOS/LVTTL interface levels. Output clock stop for Bank C. See Table 3L. LVCMOS/LVTTL interface levels. Bank B output pair. LVPECL interface levels. Output supply pins for LVPECL outputs. Bank B output pair. LVPECL interface levels. Differential Bank A output pair. LVPECL interface levels. Differential Bank A output pair. LVPECL interface levels. Differential Bank A output pair. LVPECL interface levels.
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Number 51, 53, 55, 57 52, 56 59 60 62, 63
Name QC3, QC2, QC1, QC0 VCCO_CMOS LOCK MF XTAL_OUT, XTAL_IN Output Power Output Input Input
Type
Description Single-ended Bank C outputs. LVCMOS/LVTTL interface levels. Output supply pins for LVCMOS outputs. VCXO lock state. LVCMOS/LVTTL interface levels. See Table 3M. FemtoClock-PLL feedback divider selection. See Table 3E. LVCMOS/LVTTL interface levels. Internal VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor VCC = VCCO_CMOS = 3.465V Test Conditions Minimum Typical 4 10 51 51 15 Maximum Units pF pF k k
RPULLDOWN Input Pulldown Resistor ROUT Output Impedance QC[3:0]
DEVICE CONFIGURATION
The ICS813078I is a two stage device, a VCXO-PLL stage followed by a low phase noise FemtoClock PLL multiplier stage. The VCXO-PLL stage uses a pullable crystal to lock to the reference clock. The low phase noise FemtoClock multiplies the VCXO-PLL output clock up to 491.52MHz or 614.4MHz and three independent output dividers scale the frequency down to the desired output frequencies. With a given input and VCXO frequency, the output frequency is a function of the P, MF, MV and the NA, NB and NC dividers. The P and MV are controlled by the R[2:0] control pins through the internal lookup table (LUT). The VCXO-PLL pre-divider (P) down-scales the input reference frequency fREF and enables the use of the ICS813078I at a variety of input frequencies. P and MV must be set to match the VCXO frequency: fREF / P = fVCXO / MV. For example, at the nominal VCXO frequency of 30.72MHz and if MV equals one, the input frequency must be an integer multiple of 30.72MHz (for MV = 2, the input frequency must be an integer multiple of 15.36MHz). The FemtoClock PLL stage multiplies the VCXO frequency (30.72MHz) to 614.4MHz or 491.52MHz by a multiplier MF of 20 or 16. The output frequency equals [(fREF / P) * MV * MF] / NA, NB, or NC. The NA, NB and NC dividers operate independently.
Table 3A. Input Frequency Configuration Example Table (fVCXO = 30.72MHz)
fref (MHz) 30.72 61.44 122.88 15.36 10 12.8 15 20 Input R[2:0] 000 001 010 011 100 101 110 111 Internal Dividers P 1 2 4 1 125 5 125 125 MV 1 1 1 2 384 12 256 192 fXTAL (MHz) 30.72 30.72 30.72 30.72 30.72 30.72 30.72 30.72
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Table 3B. PLL Output-Divider (NA) Configuration Table.
Inputs NA1 0 (default) 0 1 1 NA0 0 (default) 1 0 1 QAn Output Frequency (MHz) MF = 0 245.76 122.88 98.304 61.44 MF = 1 307.2 153.6 122.88 76.8
Output-Divider NA Operation 2 4 5 8 fQAn = fVCO / 2 fQAn = fVCO / 4 fQAn = fVCO / 5 fQAn = fVCO / 8
Table 3C. PLL Output-Divider (NB) Configuration Table.
Inputs NB1 0 (default) 0 1 1 NB0 0 (default) 1 0 1 QBn Output Frequency (MHz) MF = 0 491.52 122.88 98.304 61.44 MF = 1 614.4 153.6 122.88 76.8
Output-Divider NB Operation 1 4 5 8 fQBn = fVCO / 1 fQBn = fVCO / 4 fQBn = fVCO / 5 fQBn = fVCO / 8
Table 3D. PLL Output-Divider (NC) Configuration Table.
Inputs NC1 0 (default) 0 1 1 NC0 0 (default) 1 0 1 QCn Output Frequency (MHz) MF = 0 122.08 98.304 61.44 30.72 MF = 1 153.6 122.88 76.8 38.4
Output-Divider NC Operation 4 5 8 16 fQCn = fVCO / 4 fQCn = fVCO / 5 fQCn = fVCO / 8 fQCn = fVCO / 16
Table 3E. Femtoclock PLL Feedback Divider (MF) Configuration Table (fXTAL = 30.72MHz)
Input MF 0 (default) 1 Feedback Divider MF 16 20 Operation fVCO = fVCXO x 16 = 491.52MHz fVCO = fVCXO x 20 = 614.4MHz
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Table 3F. Input Reference Clock Multiplexer (REF_SEL) Configuration Table
Input REF_SEL 0 (default) 1 Operation Selects CLK0, nCLK0 differential input pair as reference frequency. Selects CLK1 single-ended input as reference frequency.
The input reference selector should be tied to logic 0, selecting the differential clock inputs, for best signal integrity and lowest phase noise
Table 3G. PLL Bypass (BYPASS) Configuration Table
Input BYPASS1 0 BYPASS0 X Operation fOUT = ((fREF / P) * MV * MF) / NA, NB, or NC. VCXO-PLL operation, jitter attenuation and frequency multiplication enabled. fOUT = ((fREF / P) * MV) / NA, NB, or NC. VCXO-PLL enabled, Femto-PLL bypassed. Jitter attenuation (VCXO-PLL) enabled. AC specifications do not apply. fOUT = fREF / NA, NB, or NC. VCXO-PLL and Femto-PLL bypassed, no jitter attenuation and frequency multiplication. AC specifications do not apply.
1
0
1 (default)
1 (default)
The BYPASS[1:0] controls should be set to logic LOW level for normal operation. BYPASS = 1x enables the PLL bypass mode for factory test. In PLL Bypass Mode, the output frequency is divided by NA, NB, or NC dividers.
Table 3H. Fast Lock Mode (FLM) Configuration Table
Input FLM 0 (default) 1 Operation Normal operation. Fast PLL lock operation. Use this mode only during startup to decrease PLL lock time.
VCC = 3.3V 0V tLOCK
VCXO-PLL Acquires Lock LOCK
VCXO-PLL Locked
FLM
Fast Lock Mode (High VCXO-PLL Bandwidth)
Nominal VCXO-PLL Bandwidth
Figure 1. Recommended Start-up Timing Diagram
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Table 3I. Reset (nMR) Configuration Table
Input nMR 0 1 (default) Operation The Femto-PLL is reset. Normal operation.
Table 3J. Output Disable (nSTOPA) Configuration Table.
Input nSTOPA 0 1 (default) Operation QA[2:0]/nQA[2:0] outputs are stopped in logic LOW state. The assertion of nSTOPA is asynchronous to the internal clock signal and may cause an output runt pulse. Normal operation and outputs enabled.
Table 3K. Output Disable (nSTOPB) Configuration Table.
Input nSTOPB 0 1 (default) Operation QB[1:0] / nQB[1:0] outputs are stopped in logic LOW state. The assertion of nSTOPB is asynchronous to the internal clock signal and may cause an output runt pulse. Normal operation and outputs enabled.
Table 3L. Output Disable (nSTOPC) Configuration Table.
Input nSTOPC 0 1 (default) Operation QC[3:0] outputs are stopped in logic LOW state. The assertion of nSTOPC is asynchronous to the internal clock signal and may cause an output runt pulse. Normal operation and outputs enabled.
Table 3M. PLL Lock Status Output (LOCK_DT) Configuration Table.
Output Conditions Locked Unlocked LOCK_DT Constantly HIGH. HIGH with occasional LOW pulses.
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VCC + 0.5V 50mA 100mA -0.5V to VCCO_CMOS+ 0.5V 31.8C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = VCCO_CMOS = 3.3V 5%, TA = -40C to 85C
Symbol VCC VCCA Parameter Core Supply Voltage Analog Supply Voltage Test Conditions Minimum 3.135 VCC - 0.15 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 260 15 6 Units V V V mA mA mA
VCCO, Output Supply Voltage VCCO_CMOS IEE ICCA ICCO_CMOS Power Supply Current Analog Supply Current Output Supply Current
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Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO_CMOS = 3.3V 5%, TA = -40C to 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK1, REF_SEL, MF, FLM, NA[1:0], NB[1:0], NC[1:0], R[2:0] nSTOP[A:C], BYPASS[1:0], nMR CLK1, REF_SEL, MF, FLM, NA[1:0], NB[1:0], NC[1:0], R[2:0] nSTOP[A:C], BYPASS[1:0], nMR VOH VOL Output High Voltage Output Low Voltage QC0:QC3 QC0:QC3 VCC = VIN = 3.465V Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 Units V V A
IIH
Input High Current
VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V IOH = -12mA IOL = 12mA
10
A
-10
A
IIL
Input Low Current
-150 2.6 0.5
A V V
Table 4C. Differential DC Characteristics, VCC = VCCO = 3.3V 5%, TA = -40C to 85C
Symbol IIH IIL VPP VCMR Parameter Input High Current Input Low Current nCLK0 Peak-to-Peak Voltage; NOTE 1 Common Mode Input Voltage; NOTE 1, 2 CLK0, nCLK0 CLK0 Test Conditions VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -10 -150 0.15 VEE + 0.5 1.3 VCC - 0.85 Minimum Typical Maximum 150 Units A A A V V
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V 5%, TA = -40C to 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs termination with 50 to VCCO - 2V.
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AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCO = VCCO_CMOS = 3.3V 5%, TA = -40C to 85C
Symbol Parameter Test Conditions R=000 R=001 R=010
fREF Input Reference Frequency
Minimum
30.72MHz-50ppm 61.44MHz-50ppm 122.88MHz-50ppm 15.36MHz-50ppm 10MHz-50ppm 12.88MHz-50ppm 15MHz-50ppm 20MHz-50ppm
Typical
Maximum
30.72MHz+50ppm 61.44MHz+50ppm 122.88MHz+50ppm 15.36MHz+50ppm 10MHz+50ppm 12.88MHz+50ppm 15MHz+50ppm 20MHz+50ppm
Units
R=011 R=100 R=101 R=110 R=111 MF=0, N=1 MF=0, N=2 MF=0, N=4 MF=0, N=5 MF=0, N=8 MF=0, N=16 MF=1, N=1 MF=1, N=2 MF=1, N=4 MF=1, N=5 MF=1, N=8 MF=1, N=16
491.52 245.76 122.88 98.304 61.44 30.72 614.4 307.2 153.6 122.88 76.8 38.4 30.72MHz-50ppm 491.52, 614.4 30.72MHz+50ppm
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ps ps ps ps ps 35 30 ps ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
fOUT
Output Frequency
fVCXO fVCO
VCXO-PLL VCO Lock Range Femto-PLL VCO Lock Range QBn RMS Phase Jitter Integration Range: 12kHz - 20MHz; NOTE 1 QAn, QBn QAn, QBn QAn, QBn QAn, QBn
491.52MHz 153.6MHz, MF=20 122.88MHz, MF=20 122.88MHz, MF=16 61.44MHz, MF=16 153.6MHz, QCn = off 122.88MHz, QCn = off 122.88MHz, QCn = off
1.03 0.92 1.1 1.1 0.97
tjit(O)
tjit(per)
Period Jitter
QAn QBn QAn, QBn 10Hz offset 100Hz offset
-41.3
N
Single-Side Band Noise at: QAn =122.88MHz
1kHz offset 10kHz offset 100kHz offset 1MHz offset
30.72MHz XTAL, fref = 30.72MHz, QBn and QCn = 122.88MHz
-71.5 -100.7 -127.2
-128.2 -131.4
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Symbol
Parameter 10Hz offset 100Hz offset
Single-Side Band Noise at: QAn = 61.44MHz
Test Conditions
Minimum
Typical -44.6 -77.2 -106.4 -132.8 -132.9 -137.9
Maximum
Units
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
N
1kHz offset 10kHz offset 100kHz offset 1MHz offset fQA = fQB fQA fQB QAn/nQAn QBn/nQBn QCn QAn/nQAn
30.72MHz XTAL, fref = 30.72MHz, QBn and QCn = 61.44MHz
tsk(o)
Output Skew NOTE 2, 3 Bank Skew; NOTE 2, 4
across QAn and QBn across QAn and QBn
200 300 50 50 65
ps ps ps ps ps ps ps ps % % % %
tsk(b)
20% to 80% 20% to 80% 20% to 80% N1 N=1
100 100 350 47 47 43 45
600 600 1050 53 53 57 55
tR / tF
Output Rise/ Fall Time
QBn/nQBn QCn QAn/nQAn QBn/nQBn QBn/nQBn QCn
odc
Output Duty Cycle
NOTE: TA, Ambient Temperature applied using forced air flow. NOTE 1: Phase jitter measured using a 30.72MHz quartz crystal. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
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Typical Phase Noise at 61.44MHz
Filter
61.44MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.97ps (typical)
Noise Power
dBc Hz
Offset Frequency (Hz)
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Raw Phase Noise Data
Phase Noise Result by adding a filter to raw data
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Typical Phase Noise at 122.88MHz
Filter 122.88MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.1ps (typical) dBc Hz Noise Power Offset Frequency (Hz)
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Phase Noise Result by adding a filter to raw data
Raw Phase Noise Data
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Parameter Measurement Information
1.65V5% 1.65V5% 1.65V5% 1.65V5%
VCC, VCCO VCCA
Qx
SCOPE
VCC, VCCO_CMOS VCCA
SCOPE
Qx
LVPECL
nQx VEE
LVCMOS
VEE
-1.65V5%
-1.65V5%
3.3V LVPECL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
VCC
nCLK0
V
PP
Noise Power
Cross Points
V
Phase Noise Mask
CMR
CLK0
VEE
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Differential Input Level
RMS Phase Jitter
VOH
nQx
VREF VOL
Qx
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
nQy Qy
Histogram
Reference Point
(Trigger Edge)
tsk(o)
Mean Period
(First edge after trigger)
Period Jitter
Differential Output Skew
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Parameter Measurement Information, continued
nQXn
QCn
VCCO 2
QXn nQXn
QCn
VCCO 2 tsk(b)
QXn
tsk(b)
Where X = Bank QAn or Bank QBn
LVCMOS Bank Skew
Differential Bank Skew
nQXn QXn
nQA0:nQA2. nQB0, nQB1 QA0:QA2. QB0, QB1
t PW
t
PERIOD
QCn
VCCO/2 tsk(bk-bk) odc =
t PW t PERIOD
x 100%
Where X = Bank QAn or Bank QBn
Output Rise/Fall Time
Differential Output Duty Cycle/Pulse Width/Period
QC0:QC3
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
LVCMOS Output Duty Cycle/Pulse Width/Period
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Application Information
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal CL is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependant on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The VCXO-PLL Loop Bandwidth Selection Table shows RS, CS and CP values for recommended high, mid and low loop bandwidth configurations. The device has been characterized using these parameters. For other configurations, refer to the Loop Filter Component Selection for VCXO Based PLLs Application Note. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components.
LF0 LF1 ISET
RS
CP CS
RSET
XTAL_IN CTUNE 30.72MHz CTUNE XTAL_OUT
VCXO Characteristics Table
Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 9.3 14.7 7.5 Units kHz/V pF pF
VCXO-PLL Loop Bandwidth Selection Table
Bandwidth 8.5Hz (Low) 85Hz (Mid) 22.2kHz (High) Crystal Frequency (MHz) 30.72 30.72 30.72 MV 384 192 1 RS (k) 20 20 30 CS (F) 10 10 0.01 CP (F) 0.1 0.01 0.00001 RSET (k) 10 2.0 2.2
Crystal Characteristics
Symbol fN fT fS CL CO CO / C1 ESR Parameter Mode of Oscillation Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25 0C
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Test Conditions
Minimum
Typical Fundamental 30.72
Maximum
Units MHz
20 20 -40 10 4 220 240 20 1 3 per year +85
ppm ppm
0C
pF pF
mW ppm
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Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input CLK
V_REF nCLK C1 0.1u
R2 1K
Figure 2. Single-Ended Signal Driving Differential Input
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS813078I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO and VCCO_CMOS should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 3 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
Figure 3. Power Supply Filtering
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 4A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK Zo = 50 Zo = 50 nCLK nCLK CLK 3.3V
LVPECL HiPerClockS Input
R1 50 R2 50
HiPerClockS Input
LVHSTL IDT HiPerClockS LVHSTL Driver
R1 50 R2 50
R2 50
Figure 4A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver
Figure 4B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
3.3V 3.3V 3.3V R3 125 Zo = 50 CLK CLK Zo = 50 nCLK R1 100 R4 125 3.3V 3.3V Zo = 50
LVPECL
R1 84 R2 84
HiPerClockS Input
Zo = 50
nCLK
LVDS
Receiver
Figure 4C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver
Figure 4D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V 3.3V 2.5V R3 120 Zo = 60 R4 120
2.5V
3.3V
*R3
33
Zo = 50 CLK Zo = 50 nCLK Zo = 60
CLK
nCLK
HCSL
*R4
33 R1 50 R2 50
HiPerClockS Input
SSTL
R1 120 R2 120
HiPerClockS
*Optional - R3 and R4 can be 0
Figure 4E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver
Figure 4F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver
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Recommendations for Unused Input and Output Pins Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
LVCMOS Outputs CLK Input
For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. All unused LVCMOS output can be left floating. There should be no trace attached.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50W transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V Zo = 50 125 FOUT FIN Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT Zo = 50 84 84 FIN 125
Zo = 50
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
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EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
SOLDER PIN EXPOSED HEAT SLUG
SOLDER
PIN
SOLDER
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 6. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS813078I. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS813078I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. Core and LVPECL Output Power Dissipation * Power (core)_MAX = VCC_MAX *IEE_MAX = 3.465V * 260mA = 900.9mW
Power (output)_MAX = 30mW/Loaded Output Pair If all outputs are loaded, the total power is 5 * 30mW = 150mW
LVCMOS Output Power Dissipation * Output Impedance ROUT Power Dissipation due to Loading 50 to VCCO/2 Output Current IOUT = VCCO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA * Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output * Total Power Dissipation on the ROUT
Total Power (ROUT) = 10.7mW * 4 = 42.8mW
* Dynamic Power Dissipation at 153.6MHz Power (25MHz) = CPD * Frequency * (VCCO)2 = 10pF * 153.6MHz * (3.465V)2 = 18mW per output
Total Power (153.6MHz) = 18mW * 4 = 72mW
Total Power Dissipation * Total Power = Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (153.6MHz) = 900.9mW + 150mW + 42.8mW + 72mW = 1165.7mW
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2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 31.8C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 1.166W * 31.8C/W = 122.1C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 64 Lead TQFP, E-Pad Forced Convection
JA Vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 31.8C/W 1 25.8C/W 2.5 24.2C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 64 Lead TQFP, E-Pad
JA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 31.8C/W 1 25.8C/W 2.5 24.2C/W
Transistor Count
The transistor count for ICS813078I is: 6235
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Package Outline and Package Dimensions
Package Outline - Y Suffix for 64 Lead TQFP, E-Pad
-HD VERSION EXPOSED PAD DOWN
Table 8. Package Dimensions for 64 Lead TQFP, E-Pad
JEDEC Variation: ACD All Dimensions in Millimeters Minimum Nominal Maximum 64 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 0.20 12.00 Basic 10.00 Basic 7.50 Ref. 4.5 5.0 5.5 0.50 Basic 0.45 0.60 0.75 0 7 0.08
Symbol N A A1 A2 b c D&E D1 & E1 D2 & E2 D3 & E3 e L ccc
Reference Document: JEDEC Publication 95, MS-026
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Ordering Information
Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 813078BYILF ICS813078BYILF "Lead-Free" 64 Lead TQFP, E-Pad Tray -40C to +85C 813078BYILFT ICS813078BYILF "Lead-Free" 64 Lead TQFP, E-Pad 500 Tape & Reel -40C to +85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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